The Dark Silicon

I was wondering why this F is coming in the above equation.  It is because of this F that the entire computing world is in trouble or at least the job’s of software developers are in trouble.  🙂

Combing through my undergraduate books  I  found a very good explanation of how the above equations come  in the Book by Sedra and Smith Section 4.10.

In his keynote address in The AMD Developer Fusion Summit (AFDS),  Jem Davies  ARM Fellow,VP of Technology, Media Processing Division, emphasized that  the current need is the current we must focus on Functionality Per Unit Cost Per Unit Energy and not  Functionality Per Unit Cost Per Unit Power. Those days are gone!

What is Dark Silicon? 

Refer to the above slide. A we are putting more transistors in a single chip, it is creating problem. The basic problem is if so many transistors are powered simultaneously on such a small area, it will generate lots of heat, which will raise the temperature of this chip and thus ultimately the chip can burn and become useless.  Therefore we will have to switch off approximately 75% of the transistors by 2014. this figure will grow to approximately to 90% by 2020. !!

These unlit transistors constitute DARK SILICON.

Higher Level Programming Abstractions for FPGAs using OpenCL

Last week Altera came up with the news of experimenting with the OpenCL on its range of FPGAs. Also not much detail is given on its website, it seems however that Altera is taking OpenCL in a big way.

In this thread I will be keeping track of OpenCL development on FPGA.

FPGAs are a popular means for faster development as compared to ASICS. In short you implement some logic in HDL and the same is burned on the FPGA fabric. However all this is still a time consuming job. It takes many weeks and months to successfully port an Application on FPGA .

So what if OpenCL can be used for FPGA development?  Surely that would be loved by software community as that would help them develop on OpenCL using standard API OpenCL-C. the idea is to implement the algorithm in C and OpenCL and port it on FPGA without actually going into HDL. This means lots of time saving.

In my opinion reconfigurable computing seems to be one of the most efficient way of computing in ear future.  As and when required you can simply increase the no. of cores on FPGA , depending upon the applications demand. For example while I am doing some HD Video processing I might want 100 cores and while using a word processor I might be happy with two cores. FPGA will come to the rescue here.

OpenCL on FPGA + CPU will be a breath of fresh air for Researchers to come up with prototypes faster and thus it will accelerate the product development cycle much quickly- after all time is money , as they say…

Please refer to this link for more detail  :


Here is another blog:

HB Organized the 2nd Faculty Development Program on Heterogeneous Computing Jointly with SRM University and AMD India Pvt. Ltd .

October 1, 2011.

The 2 days event was organized at SRM University, Chennai. More than 60 professors and research scholars attended the workshop.

The inaugural function was presided over by the Vice Chancellor of SRM University , Dr. M. Ponnavaikko, the Corporate Vice President of AMD India, Mr. Shiva Gowni and the Director of AMD India, Mr. Jay Hiremath.

After the conclusion of the inaugural ceremony, technical sessions on the concepts of OpenCL and various hands-on practice sessions were conducted by Mr. Heshsham Basit and Mr. Venkatesh Kannan to coach the participants in the area.


This slideshow requires JavaScript.